1. Field of the Invention
The present invention relates to a non-volatile memory, and more specifically to an electrically erasable and programmable non-volatile memory having a read and/or write protectable zone and an electronic system incorporating such a memory.
Electrically erasable and programmable non-volatile memories are widely used as serial access memories in video devices designed for large scale consumption because such memories make it possible to store changeable information even if the power to the device is cut off. For example, such information could be the date or time of activation and duration of recording of a television broadcast which are programmed in a video tape recorder. This data is stored in registers that are read and write accessible so that it is possible to modify them. However, in some cases, write access to these registers must be locked through software control and unlocked only through a specified program sequence. In this case, it is said that the registers are write-protected. This reduces the risk of accidental modification (and therefore loss) of the data. Such accidental modification can be due to a mistake in handling by the user or to electrical disturbances in the instrument (known as "data corruption").
2. Description of the Related Art
In certain cases, it may even be desired that modification of the contents of the protected registers should not be allowed through software control but should require a modification of the hardware configuration (e.g., input signals) of the memory. Furthermore, in most applications, the same memory must also include registers that are always write accessible for the storage of transient data. There is therefore an identified need for a non-volatile memory in which at least one zone (i.e., a group of memory registers) is write protectable.
Because memories are electronic components that are manufactured identically and in large batches in order to reduce cost, a way to customize these memories is often provided so as to give the designer of an electronic system or device that incorporates these components the freedom to organize the available memory space into different variably-sized zones, some of which may be write-protected while others are not.
For this purpose, an EEPROM-type memory has been proposed. This memory, in a schematic representation, comprises a stack of memory registers divided into two memory zones, one of which is write-protectable while the other is not. The registers are identified by an address and are accessible by the indication of this address. Typically, the first register of the memory (located in a schematic representation at the bottom of the stack) is identified by an address of zero and the last register (located in a schematic representation at the top of the stack) is identified by the address whose value corresponds to the size of the memory (i.e., the total number of registers in the memory). The values of the address registers are usually expressed in hexadecimal notation, as shown by the use of a lower case "h" following the memory address, which consists of the digits 0 to 9 and/or the letters A to F.
For example, the memory shown in FIG. 1 includes 256 registers R1 to R256 that each hold 8 bits. These registers are arranged, schematically speaking, in a stack. The capacity of the memory is therefore 256 bytes or 2048 bits (i.e., 2 Kbits). In FIG. 1, the address of a register is shown to the left of the register.
The last register R256, located at address FFh, is a special-use register. In particular, the data word that it contains has the twofold function of determining the size of the write-protected memory and making the write protection effective. In operation, the protection of a zone of memory is effective only when two conditions are met. First, there should be a specified pin of the memory taken to the logic 1 state. Second, a particular bit of a protection word contained in the last register of the memory, in this case the bit b2 (FIG. 1), should be in the logic 1 state. The state of the bits b0 and b1 of the protection word do not matter. The five most significant bits b3 to b7 of the protection word define the five most significant bits of the boundary address of the zone of the memory that is write-protected, the three least significant bits of the boundary address having arbitrarily the logic value 0. The term "boundary address" is understood to be the address of a memory register that constitutes a boundary of the memory zone concerned (i.e., the address of the first or last register of this zone).
The memory zone, between the address FFh of the last register R256 and the boundary register thus defined is then protected, for example in write mode. A memory write circuit verifies the conditions of protection of the memory zone (i.e., the state of the bit b2 of the word contained at the address FFh in the register R256 and the state of the above-mentioned pin of the memory), and compares the value of the five most significant bits of the address specified for the write operation with the value of the bits b3 to b7 of the protection word. If the value of the specified address is greater than that of the boundary address, the write operation is not performed. It can be seen that it is thus possible to obtain write protection for a zone of the memory whose size can be modified in steps of eight registers. In other words, the five most significant bits of the protection word define a block of adjacent registers (eight registers in this example), the registers of this block and the upper registers being write protected if the bit b2 of the protection word is in the logic 1 state. The memory is divided into two zones, a lower zone that is not write protected and an upper zone that is write protected when this condition is met.
This protection scheme is implemented as follows. With the word contained in the last register R256 initially having all its bits and especially the bit b2 in the logic 0 state (so that the entire memory is not write protected), the data that is to be stored in a write-protected manner is written in the registers located at the upper part of the memory (with the exception of the last register). For example, this may require five registers (giving a total of five bytes to be stored). It is therefore necessary to set apart a write-protected memory zone comprising at least five registers plus the protection register, giving a total of six. The binary word 111111xxb is then written in the last register R256. (In this binary word "111111xxb", the letter "b" indicates that the value of the word is expressed in binary notation and the sign "x" indicates that the value of the corresponding bit (here, bits b0 and b1) does not matter. The block of the last eight registers R249 to R256 of the memory, whose addresses have the same value for the-most significant bits and which form the upper zone of the memory, are then write-protected. In FIG. 1, these registers are shaded gray. The other registers, which form the lower zone of the memory, are not write-protected.
This protection principal can be extended to include memories of different capacity and/or memories that are organized differently. However, the variably-sized protectable memory zone is always located in the upper part of the memory. This is because the special-use register that receives the protection word is the last register of the memory. Typically, the first registers of the memory are often reserved for the storage of data needed to initialize the system incorporating this memory (these first registers being therefore themselves write-protected in a manner that cannot be modified by programming), and the rest of the registers are entirely left at the disposal of the user (who is the designer of an electronic system or machine incorporating the memory). Advantageously, this memory zone left to the disposal of the user, namely this zone that is not write protectable, takes the form of a block of adjacent registers (whose addresses are consecutive), thus simplifying management by programming.
Further, the size of the protected zone is defined by specifying a single boundary address, and the other boundary address must be that of the last register. This allows simplicity of verification of protection which is done prior to any write operation in the memory.
Additionally, defining the protected zone as being in the upper part of the memory between the boundary address and the address of the last register R256 (while including these addresses) then implies that the register R256 in which the protection word is stored is itself part of the protected zone. Consequently, unless the logic value present in the above-mentioned pin of the memory is modified, the size of the protected zone can no longer be modified and the protection itself can no longer be deactivated since the size and the protection are determined by the value of the binary word stored in a last register R256 and this register can no longer be modified.
However, such a memory also has drawbacks. For example, if the program that drives a system incorporating the memory has to define a protected memory zone with a specified size, then the program has to know the capacity of the memory in order to be able to deduce therefrom the boundary address whose most significant bits will constitute the most significant bits of the programming word. In other words, the boundary address that must be considered in order to define a write-protectable memory zone of a specified size is a relative address that depends on the address of the last register of the memory. And this address depends on the size of the memory (i.e., the capacity). However, the software that directs the system and, by virtue of this role, manages the different resources (and, in particular, coordinates the memory read and write operations) does not necessarily know the size of the memory or memories contained in the system. In fact, one and the same electronic system is often made into several versions: a basic version having low memory capacity and more sophisticated versions having greater memory capacities. These different versions of the electronic system therefore have memories generally belonging to one and the same family of components (so that their modes of connection and addressing are identical) but have different capacities.
While procedures have been proposed for the recognition of the capacity of the memories present in the system, these methods are complex and require substantial processing time. Such procedures are launched whenever the system is put into operation. The addressing of the memory space is still a relative addressing procedure, but the designer of the system is no longer required to take account of the capacity of the memories used to implement it. Furthermore, such procedures may themselves require the safeguarding of an initialization program that increases the requirements of the system in terms of memory space.